1. Field of the Invention
The present invention relates to memory address mapping and memory access. More particularly, the present invention relates to memory address mapping and memory access in blocks.
2. Description of Related Art
FIG. 1 illustrates a typical video decoding and display system 100. The video decoder 101 receives a data signal compressed by a video encoder and rebuilds a video frame according to the data signal. The video decoder 101 then writes the rebuilt video frame into a synchronous dynamic random access memory (SDRAM) 105 through a SDRAM controller 104. The video decoder 101 also reads the data of a reference frame from the SDRAM 105 for rebuilding the video frame. Meanwhile, a display controller 102 reads reconstructed frames from the SDRAM 105 to be displayed by a display 103. Since the video decoder 101 and the display controller 102 cannot access the SDRAM 105 at the same time, the accesses to the memory of the two should be coordinated appropriately.
The SDRAM 105 is accessed in words, and a word may be composed of 4, 8, or 16 bits. FIG. 2 is a schematic block diagram of the SDRAM 105. As shown in FIG. 2, the SDRAM 105 includes four banks, namely, banks 0˜3. Each bank includes 4K rows, and each row includes 1K words. Accordingly, a column address, a row address, and a bank address have to be appointed to access each word in the SDRAM 105.
A SDRAM requires several clock cycles for each row change so that the current row is turned off first and then the next row is turned on. Thus, row changes may reduce the bus efficiency of the SDRAM, namely, the access efficiency of the SDRAM.
The video decoder 101 decodes in macroblocks of 16×16 pixels. With general storage method, each macroblock stored in a SDRAM spans over a plurality of rows. When the video decoder 101 is rebuilding a macroblock, it may not read only one block corresponding to the reference frame; instead, it may read the data of other macroblocks adjacent to this block. Accordingly, there must be a lot of row changes at video decoding, and the number of row changes has to be reduced to improve decoding efficiency.
Besides the foregoing problem of row change, the efficiency of video encoding is also affected by address mapping conversion. The video decoder has to convert the logic address of each word in the video frame into the column address and row address of SDRAM. Complex calculations, such as table look-up and/or continuous additions and multiplications, are used in conventional techniques such as U.S. Pat. Nos. 5,668,599 and 5,910,824, which are still to be improved.